![]() Likewise, a source will wait if the destination isn’t waiting for data. This example shows the send/receive semantics that use the operators:Ĭhannel exchange is synchronized and a destination will wait until data is provided. The low-level interface is called a channel and it maps to the hardware support. There are two constructs for interprocess communication. The statement completes after completion of all three functions. Low-level parallel constructs are provided for example, par will run three functions in parallel. The xC compiler exposes the parallel programming and interprocess communication support. It’s relatively easy to adjust the code to use different pins or provide new functionality. The soft peripherals take advantage of one or more cores. The main difference is the xC compiler and the soft-peripheral support that’s covered by a collection of downloadable app notes. It exposes a little more xCORE specific hardware, but this is typical for any gdb debugger enhancements for a particular micro. Likewise, xDEBUG will be familiar to anyone using gdb. No surprises lurk when getting the development software to talk to the platform (it works with the XTAG3). The tool is also ideal for working through real-time interfaces. ![]() This complements the XTA static-analysis tool designed to address timing issues. The xSCOPE support is a real-time logic analyzer that’s very handy for applications dealing with hard real-time interface chores. The XMOS xCORE-200 eXplorerKIT features a 16-core chip with Gigabit Ethernet support. A cycle-accurate debugger called xSIM can be used to try out the architecture without needing the kit. The xDEBUG is a GDB debugger with support for xCORE. This Eclipse-based IDE incorporates the xC compiler as well as LLVM C and C++ compilers. Getting started with eXplorerKIT requires downloading the latest xTIMEcomposer Studio. The kit includes a header socket that enables use of the XTAG3 JTAG interface for low-level debugging. You can solder headers to get access to all of the chip’s pins. This has a midrange, 16-core chip with Gigabit Ethernet support. I was able to check out the programming environment for the xCORE using the xCORE-200 eXplorerKIT (Fig. Every core cycle is able to execute an instruction that pauses for an external event. Each core can issue up to two instructions per clock cycle into the execution pipeline (see “ Dual-Issue Multicore SOC Handles Soft Peripherals ”). The 32-bit cores are grouped into tiles of eight cores. XMOS's xCORE architecture supports multiple logical cores connected by an on-chip switch. The architecture is well-suited for synchronous or time-sensitive applications like audio or video processing (see “ XMOS Unveils First Software-Defined Silicon ”). That speeds response time, because a core can wait for an event instead of polling or using interrupts.Ī number of RTOS features are incorporated in the hardware, such as scheduling support. With that many cores, designers can dedicate one or more to specific interface or compute chores. The xCORE-200 family features chips with up to 32 logical cores delivering over 4000 MIPS. The xCORE architecture developed by XMOS is a bit different from most microcontrollers and microprocessors (Fig.
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